PWM (Pulse width modulation) signals, are digital signals of one bit (therefore of two levels) that are obtained from processing modulating signals. The modulating signal can be of the analog type (electrical voltage of any value between a maximum limit and a minimum limit) or of the digital type (having a value expressed as a digital number of N bits). PWM signals are often used in the area of power electronics, such as for driving a computer storage disk drive motor to accurately position the read/write heads over the portion of the disk desired to be written to or read from.
We now see how, from a digital or an analog modulating signal, one obtains a PWM signal.
Considering the case of an analog modulating signal 10, a possible method of conversion is that shown in FIG. 1. A PWM signal 12 is the result of an analog comparator 14 performing an analog comparison between the modulating signal 10 and the carrier signal 16 (typically of a triangular shape having a frequency, with respect to the modulating signal, normally higher at least by an order of magnitude). The carrier signal 16 can also be non-triangular. It can, for example, have a sawtooth profile.
In FIG. 1, one can note how, for each of value of the modulating signal 10 greater than the value of the carrier signal 16, the PWM signal 12 at the output of the analog comparator 14 assumes a logical one value. For each value of the modulating signal 10 less than the value of the carrier signal 16, the PWM signal 12 at the output of the analog comparator 14 assumes a logic zero.
Various values of the modulating signal 10 are in this way converted to a PWM signal 12 having pulses of various widths dependent on the value of the same modulating signal. Little by little the PWM signal 12 will be characterized by a certain duty cycle taken from the relationship between the duration of the logic one level (Ton) and the duration of the period of the same PWM signal (T).
The PWM signal 12 output by the comparator 14 includes a high frequency component (frequency of the carrier signal 16) and a low frequency component (the component due to the modulating signal 10). The average value of the PWM signal, little by little, is equal to Vcc times Duty-Cycle where: Vcc=the voltage value corresponding to logic level one and Duty-Cycle=Ton/T.
A digital conversion system 18 for converting a digital modulating signal 20 to a PWM signal 22 is shown in FIG. 2. The PWM signal 22 results from the comparison by a digital comparator 24 of the digital modulating signal 20 (digital number of N1 bits) and a digital carrier signal 26 (digital number of N2 bits) provided by a digital up/down counter 28.
In this particular example, the carrier signal 26 is obtained by the counter 28 counting "up" until an "end of count " (EOC) value is reached that, in this case, is equal to 2.sup.N2 -1. Upon reaching that value the counter 28 counts down until reaching the minimum possible value that, in the example, is equal to zero. Upon reaching the minimum possible value, the counter again counts "up" and so forth. A clock signal 30 is input to the counter 28 to provide timing for the counting. The period of the carrier signal 26 (taken from the time needed by the counter to count from the minimum possible value, that in the example is the value of zero, to 2.sup.N2 -1 and again until the minimum possible value) will depend on the number of bits that the counter 28 is designed to output and on the frequency clock signal 30 input to the counter.
A timing diagram of the modulating 20, PWM 22, and carrier 26 signals is provided in FIG. 3. For simplicity, the carrier signal 26 is represented with a straight line rather than a stepped line of 2.sup.N2 -1 steps.
FIG. 3 shows that, for each value of the modulating signal 20 greater than the value of the carrier signal 26, the output of the digital comparator 24 assumes a logic one value and for each of value of the modulating signal less than the value of the carrier signal, the output of the digital comparator assumes a logic zero value. Various values of the modulating signal 20 are converted in this way to the PWM signal 22 having pulse widths dependent on the value of the modulating signal. Little by little the PWM signal 22 will be characterized by a certain duty cycle taken from the relationship between the duration of the logical one level (Ton) and the duration of the period of the PWM signal (T).
Also in this case the PWM signal exiting from the digital comparator 24 includes a high-frequency component (at the frequency of the carrier signal 26) and a low frequency component (a component due to the modulating signal 20). The average value of the PWM signal, little by little, is equal to the Vcc times Duty-Cycle where: Vcc=the voltage value corresponding to logic level one (typically the supply voltage) and Duty-Cycle=Ton/T.
That result shows that the average value of the PWM signal output from the conversion circuit assumes various values according to the variations of the supply voltage. To clarify with a simple example, assume that the PWM signal 22 has a duty cycle of 50% and a supply voltage Vcc of 12 V+/-10%. When Vcc equals 10.8 V (12 V-10%), the average value of the PWM signal 22 will be 5.4 V (10.8*50%) and when Vcc equals 13.2 V (12 V+10%), the average value of the PWM signal Will be 6.6 V. Therefore, the average value of the PWM signal 22 can assume values between 5.4 V and 6.6 V.
Allowing the PWM signal 22 to vary based on the supply voltage is obviously undesirable because such a PWM signal 22 would not accurately convey the information or power sought to be conveyed by whichever system is supplying the modulating signal 20. For example, if a computer storage disk controller issues the modulating signal 20 at a particular value X in order to position the read/write head over a particular sector of the disk, if the PWM signal 22 being output based on that modulating system varies, then the PWM signal will not accurately position the read/write heads.